55 lines
1.6 KiB
Diff
55 lines
1.6 KiB
Diff
From 53d6ccbeed4c519dc105f98552067ced2ecbd432 Mon Sep 17 00:00:00 2001
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From: Michal Kubecek <mkubecek@suse.cz>
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Date: Fri, 23 Jun 2017 09:29:24 +0200
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Subject: [PATCH 3/6] vmmon: use standard definition of
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MSR_MISC_FEATURES_ENABLES if available
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The MSR_MISC_FEATURES_ENABLES macro is defined in mainline since commit
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ab6d9468631a ("x86/msr: Rename MISC_FEATURE_ENABLES to
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MISC_FEATURES_ENABLES") in v4.12-rc1.
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The MSR_MISC_FEATURES_ENABLES_CPUID_FAULT macro is defined in mainline
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since commit e9ea1e7f53b8 ("x86/arch_prctl: Add ARCH_[GET|SET]_CPUID") in
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v4.12-rc1.
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---
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vmmon-only/include/x86msr.h | 7 +++++++
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1 file changed, 7 insertions(+)
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diff --git a/vmmon-only/include/x86msr.h b/vmmon-only/include/x86msr.h
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index 3a6bfe8..904d9e9 100644
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--- a/vmmon-only/include/x86msr.h
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+++ b/vmmon-only/include/x86msr.h
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@@ -24,6 +24,7 @@
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#ifndef _X86MSR_H_
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#define _X86MSR_H_
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+#include <asm/msr-index.h>
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#define INCLUDE_ALLOW_USERLEVEL
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#define INCLUDE_ALLOW_VMX
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@@ -112,7 +113,9 @@ MSRQuery;
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#define MSR_TSC_AUX 0xc0000103
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#define MSR_BD_TSC_RATIO 0xc0000104
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+#ifndef MSR_MISC_FEATURES_ENABLES
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#define MSR_MISC_FEATURES_ENABLES 0x140
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+#endif
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/* Intel Core Architecture and later: use only architected counters. */
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#define IA32_MSR_PERF_CAPABILITIES 0x345
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@@ -612,7 +615,11 @@ typedef enum {
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/*
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* MISC_FEATURES_ENABLES bits
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*/
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+#ifdef MSR_MISC_FEATURES_ENABLES_CPUID_FAULT
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+#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULTING MSR_MISC_FEATURES_ENABLES_CPUID_FAULT
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+#else
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#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULTING 1
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+#endif
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--
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2.14.3
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